Modern electronic system has large numbers of subsystems, with millions of gates in each subsystem. Because of this, a minimal system simulation consisting of just a few of the subsystems results in a bloated and unmanageable emulation environment. For example, modern scalable multiprocessors may have hundreds or thousands of nodes. Each node may include tens of millions of gates. Testing and verifying such a system quickly becomes difficult, impeding the design process.
However, it is crucial to verify the design for proper functionality, prior to physical fabrication on an integrated circuit chip. While being tested, an HDL (hardware description language) model of a design is generated and is called a Design Under Test (DUT). This DUT is simulated using a testbench. The testbench generates a set of input test vectors and applies the vectors to the DUT. Testbench in its traditional form is described at a behavioral level and defines the environment for the DUT in its target system.
Design verification may be performed using a variety of methods. For example, software based simulators are the most commonly used tools. Software simulators have an advantage in that they can accept HDL at any level of abstraction, thus providing a way to simulate both a DUT and its testbench. However, such simulators have a disadvantage in that, for large designs, simulators typically can achieve a speed of not more than a few tens to hundreds of clock cycles per second (cps).
To increase the overall simulation speed, co-simulation approaches have been used, in which the behavioral testbench runs on a software simulator and the DUT is executed onto a reconfigurable hardware platform. The reconfigurable hardware platform may be implemented having a plurality of reconfigurable hardware elements, such as a set of general-purpose processors and/or Field Programmable Gate Arrays (FPGAs).
When a single design is executed on a reconfigurable hardware platform like an FPGA, irrespective of its size, it prevents the usage of same hardware by other designs. It further blocks the precious real-estate of the acceleration hardware platform. Most hardware designs occupy an effective area of the hardware chips equivalent to non-integer number of FPGA boards e.g. a design may occupy 70% silicon area of the actual FPGA hardware and other designs may be small i.e. may not even occupy even a single FPGA chip.
Hence, there is a strong need for a methodology and an associated system which makes efficient usage of area of a reconfigurable hardware platform and make resources available for the execution of multiple DUTs on a single testbench.